DIGITAL DESIGN / VERIFICATION
A processor, one cycle at a time.
Single-cycle RISC-V processor
A modular SystemVerilog core implementing an RV32I subset, from arithmetic and memory access to branches and jumps. Seven self-checking testbenches connect individual logic blocks to end-to-end program execution.
- 32-bit
- RISC-V datapath
- 7
- Self-checking testbenches
- 14
- Smoke-test cycles
01A / ARCHITECTURE
Following an instruction through the core
The datapath connects instruction fetch, register operands, execution, memory access, and writeback. Separate branch logic decides when execution leaves the sequential PC + 4 path.
Flexible operands
Input muxes select a register or the PC for operand A, and a register or immediate for operand B. That supports register arithmetic, address generation, and AUIPC using the same ALU.
Four writeback sources
The destination register receives an ALU result, loaded memory word, PC + 4 link address, or upper immediate. JALR clears the target’s least significant bit.
01B / VERIFICATION
A smoke test, explained signal by signal
These signals come directly from the saved simulation trace. Highlighted intervals connect memory operations and control flow to the program counter’s actual progression.
Memory and branch behavior
The test checks that a store writes 8 to memory word 0 and the following load returns 8 in x7. The taken BEQ skips PC 0x24, leaving x8 unchanged.
Links and a deterministic endpoint
The test checks link values of 44 in x9 for JAL and 64 in x13 for JALR. EBREAK at PC 0x40 raises halted; this is a simulation completion interface, not trap handling.
Inside the design +
Architecture
Program counter, instruction memory, register file, immediate generator, ALU and control, branch unit, data memory, and writeback mux. Parameterized instruction loading and deterministic reset make simulation repeatable.
Verification & scope
Checks cover arithmetic, signed comparisons, aligned LW/SW, control flow, and reset. EBREAK provides a simulation-only halt. This educational core implements an RV32I subset; FPGA synthesis and full ISA compliance are future work.
